The present invention relates to a flash memory system, and more specifically to a flash memory system capable of inputting/outputting data in units of sectors at random.
The flash memory is a non-volatile memory device that is capable of being highly integrated. The flash memory is used as a main memory in a flash memory system because the memory has a good ability to storeg data. The flash memory has been spotlighted as a highly integrated high capacitance device that is capable of replacing the existing hard disc and floppy disc. Presently, the flash memory has been widely used as a storage of portable digital electronic equipments such as cell phones, digital cameras, MP3 players, camcorders, PDA, etc.
However, the flash memory has a slow rate of inputting/outputting data compared to RAM. In reading and writing operations of flash memory, most of the delay time is used up to write data that is temporarily stored in a page buffer to a cell array, or to read out the data stored in the cell array to the page buffer.
In addition, a random access is impossible in the flash memory. To overcome the disadvantage of the flash memory, nWE methods for supporting a random access using a buffer memory in the flash memory system have been developed.
A flash memory system needs a buffer memory to store data temporarily before writing data in the flash memory or transmitting data to a host so as to support a random access. The buffer memory is a randomly accessible memory (e.g., a DRAM or an SRAM).
Meanwhile, the flash memory comprises a plurality of blocks (e.g., 1024 blocks or 2048 blocks). In the flash memory, the block is a basic unit of an operation of erasing data. One block comprises a plurality of pages (e.g., 16 pages, 32 pages or 64 pages). The page is a basic unit in operations of writing and reading data.
A size of one page is usually (512+16) bytes or (2K+64) bytes. When a size of one page is (2K+64) bytes, the 2K bytes corresponds to normal data and the 64 bytes corresponds to additional data. The normal data is stored in a main region and the additional data is stored in a spare region. In this case, the additional data means error correction and detection code data, address mapping data, hardware level data, etc. that are generated by means of the normal data.
The flash memory can be categorized into a small block flash memory and a large block flash memory according to the size of page. The small block flash memory has a page size of (512+16) bytes. The large block flash memory has a page size of (2K+64) bytes or more.
Using the large block flash memory may have a faster rate of inputting/outputting data than using the small block flash memory, since the large block flash memory may write a large amount of data to the cell array or read from the cell array at a time.
In addition, using the large block flash memory may reduce the size of a chip. The entire chip size can be effectively reduced by using one large block flash memory instead of several small block flash memories. Recently, the large block flash memory is mainly used to increase the rate of inputting/outputting data and to reduce the chip size.
However, the large block flash memory does not use the control method that is used in the small block flash memory. Especially, a unit of error correction and detection code, a spare region, and the like depend on the page size and should be adjusted to the page size. Therefore, a control method of the flash memory must be organized differently according to each of the small block flash memory and the large block flash memory. If the control method used in the small block flash memory is used in the large block flash memory, a region without data exists in the large block flash memory, resulting in reduced efficiency of storing data.